Digital Signal Processing Systems Research Articles

Design and Implementation of FIR Filters for Biomedical Applications

Abstract: Digital signal processing (DSP) greatly facilitates the continuous capture, monitoring, processing, and analysis of signals in real-world applications, particularly in biomedical or wearable devices. Within DSP systems, the design of Finite Impulse Response (FIR) filters is pivotal. In scenarios demanding intricate calculations and high precision, higher-order filters are employed. Multipliers are crucial components in filter design, consuming significant chip space and introducing extra computation overhead. Designers strive to optimize multipliers to enhance performance. In this project we are going to design pipelined based FIR filter by applying pipelining concept to the FIR filter and following the previous implementations such as the FIR filter with high accuracy compared to existing method. The proposed system architectures are known to be efficient for real signal processing, offering advantages over conventional based designs. The proposed design is anticipated to yield benefits in terms of area, power consumption, and timing performance. The synthesis and simulation of the existing and proposed designs are implemented using Cadence Virtuoso.

Design Wallace Tree Multiplier Using Reversible Gates

Abstract: Multipliers are essential components in digital circuit design. They have wide spread applications in digital signal processing and communication systems. Circuit designers in VLSI design seek compact, small scale circuits with low power consumption and minimal delay. The Wallace tree multiplier is an advanced version of tree based multipliers. Numerous algorithms have been developed to create the fastest multipliers, and the Wallace tree multiplier is one such example. It utilizes reversible compressors, full adders, and half adders. The results demonstrate that the Wallace tree multiplier using reversible gates outperforms traditional multipliers in terms of power dissipation and delay, with values of 0.027W and 29.327nS re­spectively.

Discrete linear canonical shearlet transform

In this paper, we introduce the continuous and discrete version of the linear canonical shearlet transform (LCST). The authors begin with the definition of the LCST and then establish a relationship between the linear canonical transform (LCT) and the LCST. Next, the paper derives several basic properties like Parseval’s Formula, inversion formula, and the characterization of the transform’s range. In addition to the continuous version of the transform, the authors also present a discrete version of the LCST. This discrete version allows for practical implementation and efficient computation of the transform in digital signal processing systems. Lastly, the paper establishes a frame condition for the discrete LCST, which thereby helps in establishing the reconstruction formula for the discrete LCST. The paper ends with a conclusion.

Harmonizing Innovation: A Journey through the History of Computational Music

The history of computational music traces a fascinating journey of innovation and creativity, intertwining disciplines such as computer science, mathematics, music theory, and psychology. From its inception in the mid-20th century to its current state of sophistication, computational music has evolved into a multifaceted field encompassing algorithmic composition, digital signal processing, machine learning, and interactive music systems. Pioneering works such as Roads' "The Computer Music Tutorial" and Biles' "GenJam" exemplify the early endeavors in digital sound synthesis and algorithmic composition. The roots of computational music extend back to the 1950s and 1960s with the pioneering efforts of Max Mathews, John Chowning, and Lejaren Hiller, laying the groundwork for future advancements. Technological breakthroughs in the 1970s and 1980s, including the advent of digital audio workstations and FM synthesis, further propelled the field forward. The 1990s and 2000s witnessed democratization and accessibility with the rise of affordable software tools and online collaboration platforms. Today, computational music continues to evolve with the emergence of deep learning and generative AI techniques, albeit accompanied by ethical considerations regarding copyright ownership and algorithmic bias. In conclusion, the history of computational music underscores the transformative power of technology in shaping musical expression and invites us to explore new frontiers where creativity knows no bounds.

A novel approach toward optimized image processing using sigma delta modulation

Image processing has widespread uses practically in every branch of science and arts. Processing images is more difficult than processing sound or data as there are more bits in the high pixel quality image. It requires more space to store the image, more bandwidth to transmit it, and more time and resources to process. An image's complexity may decrease if its bit size is decreased. Sigma-delta modulation, or SDM for short, is an alternative method of minimizing data-word length to compression. Digital signal processing (DSP) systems can be made simpler by using the SDM approach, which was first created for analog to digital conversion (ADC). This paper suggests a novel way to use SDM in MATLAB for improved image processing. Consequently, the suggested single-bit SDM-based image arithmetic architecture is tested and compared with the traditional image arithmetic techniques. Additionally, to see the noisy channel influence on the traditional and proposed systems, some statistical metrics are also studied at different noise variance values, such as signal to noise ratio (SNR), mean square error (MSE), and Peak SNR value. The suggested architecture for the SDM-based image arithmetic precisely matches the addition and subtraction results of the conventional design, even yielding a higher SNR and the same Peak SNR as the traditional methods. In contrast, the outcomes of division and multiplication fall within an acceptable range. For better results the over-sampling ratio (OSR), an inherent characteristic of SDM must be increased at the cost of more processing cycles. Therefore, the trade-off between fewer resources, limited transmission bandwidth, and comparatively more cycles is provided by the SDM-based technique.

FPGA Implementation of Power-efficient Multipliers for Digital Signal Processing Applications

Background:: Higher power consumption raises chip temperature because it draws more current from the power source, which directly affects how long the batteries survive in portable devices. High temperature affects the dependability and functionality of a circuit, requiring more complex packaging and cooling strategies. One of the most significant challenges in VLSI design is power consumption. The power consumption of the circuit rises with both transistor density and chip complexity. In addition, one of the essential building blocks of hardware in the majority of VLSI applications and digital signal processing systems is the multiplier. Aims and objective:: This study aimed to design and compare array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths. Methodology:: In this paper, authors designed array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths. For comparison, the VIVADO tool was used to simulate and synthesize multiplier outputs. Results:: Wallace tree multipliers resulted in 31.153mW, 13.220mW, 4.099mW, and 0.988 mW of power dissipation for 16-bit, 8-bit, 4-bit, and 2-bit, respectively. The best multiplier was designed using different logic like AOI, OAI, NAND-NAND, and NOR-NOR and was compared based on power dissipation. It was observed that 2.256mW power dissipation was observed for NOR-NOR logic, which was minimal among other logics. Conclusion:: The 4-bit Wallace multiplier using NOR-NOR logic was used for FPGA implementation, which can be used in digital signal processing applications.

PaCHNOC: Packet and Circuit Hybrid Switching NoC for Real-Time Parallel Stream Signal Processing.

Real-time heterogeneous parallel embedded digital signal processor (DSP) systems process multiple data streams in parallel in a stringent time interval. This type of system on chip (SoC) requires the network on chip (NoC) to establish multiple symbiotic parallel data transmission paths with ultra-low transmission latency in real time. Our early NoC research PCCNOC meets this need. The PCCNOC uses packet routing to establish and lock a transmission circuit, so that PCCNOC is perfectly suitable for ultra-low latency and high-bandwidth transmission of long data packets. However, a parallel multi-data stream DSP system also needs to transmit roughly the same number of short data packets for job configuration and job execution status reports. While transferring short data packets, the link establishment routing delay of short data packets becomes relatively obvious. Our further research, thus, introduced PaCHNOC, a hybrid NoC in which long data packets are transmitted through a circuit established and locked by routing, and short data packets are attached to the routing packet and the transmission is completed during the routing process, thus avoiding the PCCNOC setup delay. Simulation shows that PaCHNOC performs well in supporting real-time heterogeneous parallel embedded DSP systems and achieves overall latency reduction 65% compared with related works. Finally, we used PaCHNOC in the baseband subsystem of a real 5G base station, which proved that our research is the best NoC for baseband subsystem of 5G base stations, which reduce 31% comprehensive latency in comparison to related works.

Complex of algorithms for fast determination of the parameters of motion of high-speed vessels in the digital signal processing system of a space synthetic aperture radar

The article presents the main considerations for determining the tangential velocity of high-speed vessels in the digital signal processing system of a space synthetic aperture radar with an amplitude-phase program discriminator in the azimuth channel. The article suggests a complex of algorithms for fast determination of the parameters of motion of high-speed vessels in the digital signal processing system of a space synthetic aperture radar. The article contains the results of semi-natural experiments that confirm the reliability of the algorithms and their effectiveness in solving the problem of observing the sea surface.

Fault Classification and Diagnosis Approach Using FFT-CNN for FPGA-Based CORDIC Processor

Within the realm of digital signal processing and communication systems, FPGA-based CORDIC (Coordinate Rotation Digital Computer) processors play pivotal roles, applied in trigonometric calculations and vector operations. However, soft errors have become one of the major threats in high-reliability FPGA-based applications, potentially degrading performance and causing system failures. This paper proposes a fault classification and diagnosis method for FPGA-based CORDIC processors, leveraging Fast Fourier Transform (FFT) and Convolutional Neural Networks (CNNs). The approach involves constructing fault classification datasets, optimizing features extraction through FFT to shorten the time of diagnosis and improve the diagnostic accuracy, and employing CNNs for training and testing of faults diagnosis. Different CNN architectures are tested to explore and construct the optimal fault classifier. Experimental results encompassing simulation and implementation demonstrate the improved accuracy and efficiency in fault classification and diagnosis. The proposed method provides fault prediction with an accuracy of more than 98.6% and holds the potential to enhance the reliability and performance of FPGA-based CORDIC circuit systems, surpassing traditional fault diagnosis methods such as Sum of Square (SoS).

4:2 Compressor Design for Low Leakage Applications in FinFET Technology

ABSTRACT The increased short-channel effects in the ultra-nanoscale regime limit the operation of complementary metal oxide semiconductor (CMOS) technology for future systems. To combat the issues in the ultra-nanoscale regime, fin-shaped field effect transistor (FinFET) technology is the best choice because of its numerous advantages over CMOS technology. FinFET enhances the further scaling of the devices and control over the channel. Therefore, this research paper presents the implementation of a low leakage 4:2 compressor in FinFET technology. A compressor is a general block, especially used in multiplier units and hence in digital signal processing (DSP) systems. The design of the low power compressor improves the overall efficiency of the DSP systems. An extensive study of the proposed low power 4:2 compressor at 7 nm technology node is done in the paper. Mentor Graphics tools are used for the circuit simulations and analyzes. The key parameters, such as leakage power, delay, power delay product (PDP), and the process voltage temperature (PVT) variations, are estimated for the performance evaluation. The proposed 4:2 compressor saves 87.33% of leakage power and is 75.90% more energy efficient compared to its conventional counterpart.

Review on Advances in VLSI Multipliers

This abstract explores recent advancements in multiplier design, addressing the critical factors of speed, power consumption, and layout regularity. The emphasis is on achieving optimal trade-offs to meet the increasing demands of high-performance digital systems. As digital signal processing (DSP) systems continue to evolve, the reliance on hardware multiplication becomes paramount for achieving high data throughput. The presented advancements in multiplier design contribute to the development of compact, high-speed, and low-power Very Large-Scale Integration (VLSI) implementations, catering to the diverse needs of modern digital systems.

Analytical method of DC input impedance for stability analysis of IPM motor drive system

AbstractThis paper proposes an analytical calculation method of frequency characteristics of DC input impedances of an IPM motor drive system for design and stability analysis by the impedance method. The proposed method is based on an averaged frequency model linearized at an operating point. The developed small‐signal model considers control principles and mechanical perturbations. It is an analog and digital mixed model which is controlled by a digital signal processor system. Analysis examples of frequency characteristics for the impedance method by the proposed method are investigated and validated analytically and experimentally.

VLSI Implementation of 3-Parallel FIR Filters through Coefficient Symmetry Property and Fast FIR Algorithm

In multirate digital signal processing systems, polyphase filters are frequently used. The challenges in multirate digital signal processing systems primarily relate to efficiently processing signals at different rates while maintaining high-quality output. These challenges include computational complexity, power consumption, and signal delay. The coefficient symmetry property plays a key role in systematically arranging of filter taps in symmetric manner to improve operating efficiency. With a major focus on using the coefficient symmetry characteristic, this paper addresses the VLSI implementation of traditional Type-1 polyphase FIR filters. Furthermore, this paper incorporated 3-parallel FIR filters especially for sequences with odd lengths in order to take full advantage of the coefficient symmetry characteristic. The Fast FIR Algorithm (FFA) method is used to increase overall efficiency. Furthermore, in order to achieve better performance, a modified FFA technique is introduced to enhance overall performance. The paper thoroughly investigates important VLSI factors, such as power consumption, utilization, and delay, and shows how, by utilizing coefficient symmetry and applying this modified FFA technique, filters that are optimized for both power consumption and area utilization are able to be implemented. The results illustrate a significant reduction in both area and power consumption, particularly for longer filters, attributed to the reduced number of multiplication operations inherent in the fast FIR algorithm approach. Additionally, image processing application using 3x3 FIR filter is executed.

Development of a high-speed digital pulse signal acquisition and processing system based on MTCA for liquid scintillator neutron detector on EAST

Development of a high-speed digital pulse signal acquisition and processing system based on MTCA for liquid scintillator neutron detector on EAST

Analysis of System Capacity and Spectral Efficiency of Fixed-Grid Network

In this article, the performance of a fixed grid network is examined for various modulation formats to estimate the system's capacity and spectral efficiency. The optical In-phase Quadrature Modulator (IQM) structure is used to build a fixed grid network modulation, and the homodyne detection approach is used for the receiver. Data multiplexing is accomplished using the Polarization Division Multiplexed (PDM) technology. 100 Gbps, 150 Gbps, and 200 Gbps data rates are transmitted under these circumstances utilizing various modulation formats. Various pre-processing and signal recovery steps are explained by using modern digital signal processing systems. The achieved spectrum efficiencies for PM-QPSK, PM-8 QAM, and PM-16 QAM, respectively, were 2, 3, and 4 (bits/s)/Hz. Different modulation like PM-QPSK, PM-8-QAM, and PM-16-QAM each has system capacities of 8-9, 12-13.5, and 16-18 Tbps and it reaches transmission distances of 3000, 1300, and 700 kilometers with acceptable Bit Error Rate (BER≤ 2× 10-3 ) respectively. Peak optical power for received signal detection and full width at half maximum is noted for the different modulations under a fixed grind network.

A Nonlinear Function Logic Computing Architecture With Low Switching Activity

Nonlinear functions are widely involved in modern digital signal processing systems, which are usually calculated by polynomial approximation, CORDIC algorithm, or look-up tables. Due to the quite complex logic computing architectures, these methods suffer from high switching activity of logic elements, resulting in tremendous dynamic power consumption. Reducing the switching activity is believed an efficient way to save dynamic power. In this brief, we first analyzed and proved the low switching activity feature of the conventional unary number representation. Afterward, a novel multi-hot unary number representation method and the corresponding logic computing architecture with low switching activity are proposed for nonlinear function, which significantly reduces switching activity and power consumption. Moreover, the proposed nonlinear function logic computing architecture is extended to single input multiple output nonlinear function calculation, which shares the multi-hot encoder to further reduce the hardware cost. According to the post-synthesis power evaluation using PrimePower tools, the proposed architecture achieves significant switching activity and dynamic power reduction compared to conventional computing architectures.

Quantization error for weak RF simultaneous signal estimation

In a congested signal environment, it is difficult to obtain estimates of weak RF signal parameters. Determining signal parameter estimates in real time is a challenge for electronic warfare receivers that aim to receive multiple simultaneous signals. Prior work provided estimates of weak signal parameters (weak signal frequency and weak signal amplitude) without taking into account any error introduced by analog-to-digital converters that are inherently part of digital signal processing systems. In order to obtain realistic estimates, we need to take error introduced by an ADC into account. The primary aim of this paper is to quantify error introduced by a single ideal ADC as a function of angle. This paper presents a method to estimate angle resolution and quantization levels in N-bit analog-to-digital converters (ADCs) for use in a weak radiofrequency (RF) simultaneous signal estimation process. The paper quantifies the error in the angle quantization of an N-bit ADC for an input complex signal that is the instantaneous frequency obtained for the situation in which there are two simultaneous signals (with one strong signal and one weak signal) in a weak RF simultaneous signal estimation process. The presented method describes the process to determine the angle quantization range, angle quantization uncertainty, and angle quantization error. This approach has potential applications in electronic warfare (EW) systems. The approach also has potential for assessing ADC performance for measurements that approach the quantum limit. Results are presented for 1-bit, 2-bit, 3-bit, and 10-bit ADCs.

Design of a Digital Array Signal Processing System with Full Array Element

For the application of a digital array signal processing system with a high sampling rate and large bandwidth, and considering the constraints of limited resources (performance, volume, power consumption, weight, etc.), this paper proposes a design and implementation method of broadband digital array signal processing system based on radio frequency system on a chip. The system focuses on multi-channel synchronization under a high sampling rate and multi-channel amplitude and phase calibration under large bandwidth to form an all-digital, low-power, multi-channel, high-speed, large bandwidth hardware platform suitable for broadband digital array signal processing. Through the implementation of the Multiple-Input Multiple-Output phased-array digital beamforming algorithm, the test conducted verifies that the system has superior signal processing performance of the broadband digital array.

Implementation of a Butterworth digital filter using Python libraries

Formulation of the problem. In digital signal processing, noise refers to unwanted or random elements of a signal that can distort or corrupt its information content. Such noise can arise from various sources, including electromagnetic interference, thermal noise, quantization errors, and degradation of the transmission channel. It is necessary to deal with noise in a digital signal, as it can degrade the quality and reliability of the signal, lead to errors, distortions and loss of information. Moreover, noise can limit the performance of many digital signal processing systems, such as communications and audio processing systems. Therefore, various methods and algorithms have been developed to reduce noise and improve the quality of digital signals, the main of which is filtering. Target. Increasing the efficiency of digital signal processing systems using filters that allow you to programmatically change the signal filtering parameters. Development of a signal processing system in the Python programming language that implements the Butterworth digital filter algorithm. Results. The architectures of filters with infinite impulse response (IIR filters), features of the Butterworth filter are considered. A software model of a Butterworth digital filter in the Python programming language has been developed, and its verification has been carried out in relation to an audio file. The work of the model is based on the use of Python libraries such as Matplotlib, SciPy and Librosa, which allow you to implement the required algorithm and get the visualization of the signal. Practical significance. The results obtained can later be used as a module of a programmable universal digital signal processing system.

Development of an intelligent dual-beam gamma densitometer for real-time recognition of two-phase flow regime in horizontal pipe

This work includes the hardware and software development of a high sampling rate dual-beam gamma densitometer for real-time two-phase flow monitoring. The designed densitometer consists of two fast SiPM-based gamma detectors and a custom embedded system for digital signal processing and running flow regime recognition neural network. An exclusive LSTM deep neural network has been developed to classify flow regimes into six classes including stratified, annular, bubbly, wavy, slug, and plug. Therefore, the proposed design is superior to the traditional approaches by (i), unifying signal processing and flow identification units into a single cost-effective embedded system; (ii), reducing the need for time-consuming signal preprocessing steps from conventional to feed-forward neural networks, and (iii), real-time identification of the flow due to the high refresh rate of the data processing chain. The optimal neural network model has been obtained through comprehensive sensitivity analyses to have the best interpolation and generalization. The experimental evaluations showed that the optimized model recognizes the flow regime based on 6 s of gamma data sequence with an accuracy of ∼92%–97% depending on the flow regime in the pipeline. Furthermore, the real-time experiment proved the successful performance of the densitometer to trace the flow regime across the two-phase flow map.